Dive into the cutting-edge worlds of technology and science with Dwarkesh Patel's meticulously researched interviews that bring together brilliant minds to unpack revolutionary ideas in AI, biotech, and beyond. Each episode delivers profound, thought-provoking conversations that challenge conventional wisdom and illuminate the paths shaping humanity's future.

Dwarkesh Podcast

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Impact of political resistance on AI infrastructure development

Evaluating the effectiveness of net-zero targets in corporate sustainability

Strategies for integrating data centers into the power grid

What role can data centers play in stabilizing the power grid?

Are current net-zero targets sufficient for meaningful corporate sustainability?

How do you see political resistance affecting AI infrastructure projects?

Contrary to expectations of rapid depreciation due to technological advancements, an H100 GPU is worth more today than three years ago because it can now run more advanced AI models that generate significantly higher value, such as GPT-5.4 compared to GPT-4. This dynamic highlights how compute value increases with model improvements in a capacity-constrained environment, benefiting early committers like OpenAI over more conservative players like Anthropic.

By 2030, the primary bottleneck for scaling AI compute will shift to ASML's EUV lithography tools, with production limits potentially capping cumulative AI chip capacity at around 200 gigawatts, challenging ambitious goals like Sam Altman's vision of deploying a gigawatt per week amid the ongoing AI boom.

Despite ambitious demands for massive AI compute scaling, such as Elon Musk's 100 gigawatts per year by 2028, the semiconductor supply chain lags far behind due to insufficient AGI-driven production ramps and architectural inefficiencies, making reliance on older 7nm processes inadequate for bridging the gap. This highlights a critical bottleneck in AI advancement, where performance differences between chip generations can reach 20x due to networking and data movement constraints, not just raw FLOPS.

Why is TSMC allocating the majority of its 3nm process capacity to Nvidia rather than diversifying among competitors like Google or Amazon to fracture the market and maintain leverage?

What prevents ASML from significantly increasing its production of EUV tools beyond 100 per year by 2030, despite the explosive demand for AI chips?

Given the compounding performance advantages of newer chip architectures, what fraction of the demanded AI compute could realistically be achieved by repurposing older 7nm fabs, and under what economic conditions would this become viable?

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